Boundary Scan, also known as JTAG, is a test technique that is applied to devices equipped with a special Test Access Port (TAP) and additional circuitry. Conforming to the IEEE 1149.1 standard, these devices can be tested both internally and externally using serial data conforming to the standard.
In addition to a standard basic Boundary Scan capability to test the continuity between the internal logic and the external network on the circuit board, a fully 1149.1 compliant Boundary Scan solution can be integrated into our equipment system. Diagnosys is a Technology Partner with XJTAG, which enables us to provide an industry leading solution for testing devices and boards fitted with Boundary Scan devices.
XJTAG provides advanced graphical software:
| XJAnalyser for automatically analysing scan: | XJDebug for the debug of test code, including: | XJRunner a complete graphical run-time: | XJEase giving high-level device-centric: |
|---|---|---|---|
| Chain configurations | Breakpoints and modifications | Production environment | Software capabilities for testing non-Jtag |
| Plug-and-play configuration | Step through or over code a line at a time | Complete graphical run-time | Device from the scan chain |
| Control the pins on JTAG devices | Set, remove and display breakpoints | Environment run-only environment | High-level BASIC-type language |
| Run SVF files | Check or modify the values | Device-centric, not board-centric | |
| JTAG Chain Debugging | Non-JTAG device testing | ||
| Pin Watch | |||
| Run Chains / Single Step | |||
| After Dev | |||
| Device Geometry |